The present invention relates to an improvement in field emission display (FED) technology and, in particular, to a FED cathode assembly that substantially reduces or eliminates the occurrence of an adverse chemical reaction between a chromium gate electrode and an insulating (i.e., dielectric) oxide layer.
FIG. 1 illustrates a typical FED structure 10, which includes a cathode assembly 9 and an anode assembly 8 separated from each other by spacers 25. Cathode assembly 9 has a substrate or baseplate 12 with a base conductive layer 14 formed thereon, a resistive layer 15 (e.g., amorphous silicon) deposited on top of layer 14, and a plurality of conical, cold cathode emitters 16 formed on layer 15. Also formed on layer 15 is an electrically insulating (i.e., dielectric) layer 18 having a conductive layer located thereon, which forms gate electrode 20. This electrode, which is typically formed from metal, functions as an extraction grid to control the emission of electrons from emitters 16.
Anode assembly 8 has a transparent faceplate 22, a transparent conductive layer 23 over faceplate 22 and a black matrix grille (not shown) formed over layer 23 to define pixel regions. A cathodoluminescent coating (i.e., phosphor) 24 is deposited on these defined regions. This assembly is positioned a predetermined distance from emitters 16 using spacers 25. Typically, a vacuum exists between emitters 16 and anode 8.
A power supply 26 is electrically coupled to conductive layer 23, electrode 20 and conductive layer 14 for providing an electric field that causes emitters 16 to emit electrons and accelerate the electrons toward conductive layer 23. A vacuum in the space between baseplate 12 and anode 22 provides a relatively clear path for electrons emitted from emitters 16. The emitted electrons strike cathodoluminescent coating 24, which emits light to form a video image on a display screen created by anode 8.
FIG. 2 is a schematic diagram of a portion of the FED structure 10 shown in FIG. 1. In operation, electrons flow from the conductive layer 14 to an emitter 16 through resistor 32, which is formed by the resistive layer 15. This resistive layer is current limiting. Even in the case of a short circuit between emitter 16 and electrode 20, resistive layer 15 limits the flow of current, and thus the flow of electrons, through the circuit branch formed by conductive layer 14, resistive layer 15, and emitter 16.
Referring again to FIG. 2, an electric potential placed on gate electrode 20 (which functions as an extraction grid) pulls an electron emission stream from emitter 16. A second potential placed on layer 23 attracts the freed electrons, which accelerate toward this layer until they strike cathodoluminescent coating 24. Specific examples of FEDs are disclosed in the following U.S. patents, each of which is hereby incorporated by reference in its entirety for all purposes: U.S. Pat. Nos. 3,671,798, 3,970,887, 4,940,916, 5,151,061, 5,162,704, 5,212,426, 5,283,500, and 5,359,256.
Successful FED operation depends upon, among other things, a dependable gate electrode that is capable of consistent and prolonged operation. The formation of conventional gate electrodes is well known and described, for example, in the following U.S. patents, each of which is hereby incorporated by reference in its entirety for all purposes: U.S. Pat. Nos. 5,186,670, 5,299,331, 5,259,799 and 5,372,973.
Chromium metal is considered an ideal gate electrode in field emission displays. Although the electrical conductivity of chromium (Cr) is less than aluminum and the noble metals, critical parameters such as chemical durability, adhesion to glass and nonreactivity with solutions such as "Piranha" (i.e., a 2:1 mixture of H.sub.2 SO.sub.4 and H.sub.2 O.sub.2, commonly used to remove organic contamination and strip photoresist) and hydrofluoric acid (an aqueous solution of HF commonly used to etch SiO.sub.2) make chromium an attractive candidate for gate electrodes. In a conventional FED structure, such as shown in FIG. 1, electrodes formed from Cr layers (e.g., base conductive layer 14 and the conductive layer forming gate electrode 20) are sputter deposited to a thickness of approximately 200 nm. An insulating layer of SiO.sub.2 located between these layers (e.g., dielectric layer 18) is deposited to a thickness of about 500 nm.
It has been observed that chromium used as a gate electrode (e.g., electrode 20) adversely reacts with deposited silicon dioxide (SiO.sub.2 ; e.g., dielectric layer 18) upon application of an electrical potential between the gate electrode and a base conductive layer (e.g., layer 14), both in ambient and under vacuum conditions. Under ambient atmospheric pressure, the reaction occurs rapidly and results in a brown, bubbling reaction product at the surface of the chrome electrode. This reaction coincides with a rapid reduction in the breakdown voltage of the dielectric layer. Under vacuum conditions typical of an FED operating environment (i.e., about 1.times.10.sup.-7 to 1.times.10.sup.-8 Torr; referred to herein as "FED vacuum conditions"), no bubbling is observed on the chrome electrode, however, a gradual chemical transformation occurs at a site on the electrode where electrical contact is made with a probe tip (i.e., a standard tungsten probe tip commonly used for contacting structures during electrical measurements). Again, this reaction coincides with a gradual deterioration of the dielectric breakdown voltage.
Deterioration of dielectric breakdown voltage of a FED cathode assembly under FED vacuum conditions could lead to shorting between the Cr gate electrode and an associated base conductive layer, degradation in emission current of emitters (e.g., cold cathode emitters 16), reduction in brightness of an associated FED display and eventual failure of the FED unit. Accordingly, the very reliability of a FED unit is jeopardized by this phenomena.
From the above, it is seen that a method and apparatus is desired for substantially reducing or eliminating the occurrence of an adverse chemical reaction between a chromium gate electrode and an insulating (i.e., dielectric) layer that coincides with a deterioration of dielectric breakdown voltage in a FED cathode assembly.